In the semiconductor industry, there is a continuing trend toward higher device densities. To achieve these high densities, there has been and continues to be efforts toward scaling down device dimensions (e.g., at submicron levels) on semiconductor wafers. In order to accomplish such high device packing density, smaller and smaller feature sizes are required in integrated circuits (ICs) fabricated on small rectangular portions of the wafer, commonly known as dies. This can include width and spacing of interconnecting lines, spacing and diameter of contact holes, surface geometry such as comers and edges of various features as well as surface geometry of other features. To scale down device dimensions, more precise control of fabrication processes are required. The dimensions of and between features can be referred to as critical dimensions (CDs). Reducing CDs, and reproducing more accurate CDs facilitates achieving higher device densities through scaled down device dimensions and increased packing densities.
The process of manufacturing semiconductors or ICs typically includes numerous steps (e.g., exposing, baking, developing), during which hundreds of copies of an integrated circuit may be formed on a single wafer, and more particularly on each die of a wafer. In many of these steps, material is overlayed or removed from existing layers at specific locations to form desired elements of the integrated circuit. Generally, the manufacturing process involves creating several patterned layers on and into a substrate that ultimately forms the complete integrated circuit. This layering process creates electrically active regions in and on the semiconductor wafer surface.
The accuracy with which an image can be positioned on the surface of a wafer is quantified utilizing a minimum registration tolerance. The registration tolerance is based in large part upon the uncertainty that exists in overlaying a second masking level over a first masking level. The inability to perfectly overlay two layers may be due to several factors such as the mask making equipment, temperature differences between times of exposure that can cause mask expansion or contraction and limitations on the registration capability of the alignment tool.
Alignment accuracy and overly accuracy both provide information about the maximum error that will exist between the position of a level one pattern and a position of a level two image (which is desired to be exactly superimposed on the level one pattern. Alignment accuracy specifies the location of the alignment marks. Once it has been determined that the wafer has been aligned with a reticle as well as possible, the alignment error in the position between the two levels is determined by the inaccuracies of the stepper's alignment system.
In contrast, overlay accuracy refers to the error in position between the reticle image and the pattern on the wafer at any point on the wafer, not just where the alignment marks are made. Significant overlay errors can exist even if alignment is perfect due to errors that can exist outside of the alignment system such as lens distortions, chuck induced wafer distortions and errors in the placement of the image on a reticle.
Since all of the features on a circuit must overlay each other to within accepted tolerances, the actual overlay error of a lithography process will determine the yield and performance of the fabricated chips. If the total overlay error exceeds the tolerance that was designed into the dimensions of the chip pattern, yield will be reduced.
Alignment of one pattern layer to a previous layer is done with the assistance of special alignment patterns created on both the wafer and each reticle pattern. The procedure of aligning the reticle pattern to previously created features on the wafer involves moving the wafer stage until the reticle alignment marks coincide with the alignment marks in the wafer. Once this is accomplished, it is assumed that the circuit patterns on the reticle are correctly aligned to the features previously fabricated on the wafer (within the allowed overlay tolerance).
Overlay error is defined as the planar distance from the center of the overlay target on the wafer level in “level N” to the center of the image of the overlay target in the resist in “level N+1.” Alignment and overlay errors in semiconductor technology are expressed in terms of their x and y components. Thus, if a histogram is made of the x-axis overlay error at many points across the wafer, the result will be roughly a Gaussian distribution of overlay errors. The number quoted as the x-axis overlay (or alignment error) is the absolute value of the mean error plus three times the standard deviation of the distribution about the mean. That is, the x-axis overlay error, Overlayx, would be expressed as: Overlayx=(|X|+3σx). The y-axis overlay and alignment errors are described using the same form.
The impetus to reduce total overlay error is that if a smaller overlay error can be achieved, one can use tighter tolerances for designing circuit patterns For example, a smaller metal pitch can be used, which in many cases is an important determinant in device die size. Die size in turn is a major factor in the overall cost of producing a given circuit, since die size indicates how many parts can be made on each wafer. If the design rules do not make sufficient allowance for the overlay error, then a high percentage of the devices may fail. Overlay errors vary from one stepper to another, and wafers on a process line may be processed interchangeably on any of the steppers. This means that the tolerance inherent in the design rules must take into account the envelope of performance for all the steppers in a given fabrication.
The total process overlay budget includes all sources of error found in the lithography process, including stepper stage and lens variations, resist applications and develop variations, wafer non-uniformities, and measurement errors. The task of the overlay measurement tool is to quantify the magnitude of error arising from each of the sources and to verify the reduction of this error as process improvement develops.
There are two main functions of the overlay measurement in the fabrication of ICs. The first is to monitor the performance of lithographic alignment procedure. To do this wafers are sampled from each lot to statistically assess the overlay performance of the lot. The second function of overlay measurements is to assist in the setup of the lithography process. Overlay measurements help optimize the stepper systems when they are initially installed, and they are later used to maintain optimal stepper performance by evaluating overlay on a periodic basis.
Overlay is measured by simply printing one pattern on one level and a second pattern on a consecutive level, then measuring (on a stand-alone metrology system), the difference in the position, orientation and distortion of the two patterns. If both patterns are printed on the same exposure tool the result is tool-to-itself overlay. If they are printed on two different exposure tools the result is tool-to-tool overlay.
Alignment marks are typically specific to the stepper that is employed to perform a lithography process. Simple cross patterns were often used in earlier IC processes, but now the marks typically resemble grating patterns, with structures extending in orthogonal x and y directions.
A number of alignment strategies have been utilized in an attempt to bring the patterns on the wafer of each exposure field into satisfactory alignment with the pattern on the reticle. One method is two-point global alignment which employs two marks, spaced several inches apart. The alignment of the first mark on the wafer to its corresponding mark on the reticle ensures that the wafer and reticle are aligned to the correct x and y positions. By aligning the second set of marks it is ensured that the wafer and reticle patterns are also aligned at the same rotational angle, θ. After these two alignments are completed, the wafer is “blindstepped” to all of the exposure fields, relying on the precision of the stage movements to bring each exposure field into correct alignment. This strategy can thus be successful only if the stage orthogonality is very good and error between fields is very small and stable over time.
A second alignment strategy is called global mapping alignment. In this method, the stepper acquires the x and y positions of 5 to 10 alignment marks and then it computes a least squares fit to the data. That is, the error of each measurement is averaged out over N measurements, so the net placement error is the error of one alignment divided by the square root of N. Based on the errors computed, corrections to the intrafield and stepping parameters (interfield) of the system are made (e.g. the exposure positions of each site are corrected with reference to the computed data). These corrections are assumed to be stable for the 1 or 2 minutes needed to expose the wafer.
Leading semiconductor device manufacturers continue to shrink feature sizes to 100 nm technology node and beyond. The problem is traditional critical dimension (CD) metrology techniques such as critical-dimension scanning electron microscopy (CD-SEM) and conventional (CCD imaging) optical metrology lack the resolution required to provide accurate data about feature critical dimensions and profile. A significant limitation is that these methods provide only a top-down view of features and provide little or no data about characteristics of the side or bottom of the structure.
As CD requirements are smaller and smaller, what is needed is a system and methodology utilized to facilitate smaller components on a semiconductor chip. In order to increase component density, a more accurate methodology and system can be employed to place components more accurately to decrease errors associated with inaccurate measurement made in multiple axes employing overlay metrology, CD-SEM and defect/film thickness alignment marks.